1. Technical Field
The present invention relates to computers and, in particular, to mechanisms for controlling the rate at which power supply current changes in a microprocessor.
2. Background Art
Modern processors include extensive execution resources to support concurrent processing of multiple instructions. A processor typically includes one or more integer, floating point, branch, and memory execution units to implement integer, floating point, branch, and load/store instructions, respectively. In addition, integer and floating point units typically include register files to maintain data relatively close to the processor core. One drawback to providing a processor with extensive execution resources is that significant amounts of power are required to run them. Different execution units may consume more or less power and draw more or less current, depending on their size and the functions they implement, but the net effect of packing so much logic onto a relatively small process chip is to create the potential for significant power supply and power dissipation problems.
Few programs require the full range of a processor""s execution resources for significant time intervals. The power dissipated running a program depends on the nature of its component instructions and their potential for being executed in parallel. Programs typically include a variety of instruction types, but it is rare that enough instructions of the correct type are available to keep all of the processor""s execution resources busy for significant time periods. For this reason, most processors employ a clock gating mechanism to cut off the clock delivered to execution resources when they are not being used. In addition, different components of an execution resource can be turned on and off as instructions enter and exit the pipe stage serviced by the component. Clock gating reduces power consumption, but it can also cause rapid changes in the current provided to the processor. These current changes can alter the voltage at which the processor logic operates.
Clock signals are typically delivered to the processor""s execution resources through a clock distribution network. The clock signal is used to synchronize the charging and discharging of nodes in the processor logic between supply voltage levels, e.g, Vcc and ground. The logic is designed to operate within specified ranges of these voltage levels, which are maintained by a regulated power supply. Sudden changes in the current drawn by the processor as functional units are gated on or off, can cause these supply voltages to vary. The voltage variations are due to the finite response time of the power supply as well as reactive (inductive and capacitive) elements in the power distribution network. If the voltage variations fall outside the specified range, they can damage circuits (for voltage excursions above a maximum safe value) or create errors (for voltage excursions below a level necessary to guarantee correct operation of the logic).
The significance of these voltage excursions is determined by the rate at which the current provided to the processor by the power supply changes (xe2x80x9ccurrent change ratexe2x80x9d or xe2x80x9cdi/dtxe2x80x9d) and the electrical properties of the distribution network. For processors that implement clock gating, the current change rate depends on both the size of the current change and the time scale over which it occurs. The latter is determined by the operating frequency of the processor. The former depends on the amount of current consumed by the functional unit(s) being gated. For example, floating point multiply units are notoriously power-hungry execution resources in processors. The change in the processor""s current demand as these units are gated on and off can move the reference voltage temporarily outside its specified range.
Currently available processors offer no control over di/dt. One strategy contemplated for future processors forces a minimum level of activity to ensure that any current changes are relatively small. As processor frequencies increase, the time interval over which these current changes occur decreases, and even small current changes may affect the supply voltages. On the other hand, the use of power reduction strategies like clock-gating is increasing as processor frequencies (and power consumption) increase. Forcing minimum activity levels artificially raises power consumption levels, which partially offsets the benefits of clock gating.
The present invention addresses these and other deficiencies of available power throttling mechanisms.